View MT58L1MY18D_2039340.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance 16mb syncburst ? sram features ? fast clock and oe# access times ? single +3.3v 0.165vor 2.5v 0.125v power supply (v dd ) ? separate +3.3v or 2.5v isolated output buffer supply (v dd q) ? snooze mode for reduced-power standby ? common data inputs and data outputs ? individual byte write control and global write ? three chip enables for simple depth expansion and address pipelining ? clock-controlled and registered addresses, data i/os and control signals ? internally self-timed write cycle ? burst control (interleaved or linear burst) ? automatic power-down ? 100-pin tqfp package ? 165-pin fbga package ? low capacitive bus loading ? x18, x32, and x36 versions available options tqfp marking* ? timing (access/cycle/mhz) 3.5ns/6ns/166 mhz -6 4.0ns/7.5ns/133 mhz -7.5 5ns/10ns/100 mhz -10 ? configurations 3.3v v dd , 3.3v or 2.5v i/o 1 meg x 18 MT58L1MY18D 512k x 32 mt58l512y32d 512k x 36 mt58l512y36d 2.5v v dd , 2.5v i/o 1 meg x 18 mt58v1mv18d 512k x 32 mt58v512v32d 512k x 36 mt58v512v36d ? packages 100-pin tqfp (3-chip enable) t 165-pin fbga f ? operating temperature range commercial (0oc to +70oc) none *see page 34 for fbga package marking guide. part number example: MT58L1MY18Dt-7.5 MT58L1MY18D, mt58v1mv18d, mt58l512y32d, mt58v512v32d, mt58l512y36d, mt58v512v36d 3.3v v dd , 3.3v or 2.5v i/o; 2.5v v dd , 2.5v i/o, pipelined, double-cycle deselect general description the micron ? syncburst ? sram family employs high- speed, low-power cmos designs that are fabricated using an advanced cmos process. microns 16mb syncburst srams integrate a 1 meg x 18, 512k x 32, or 512k x 36 sram core with advanced synchronous peripheral circuitry and a 2-bit burst counter. all synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock in- put (clk). the synchronous inputs include all addresses, all data inputs, active low chip enable (ce#), two additional chip enables for easy depth expansion (ce2, ce2#), burst control inputs (adsc#, adsp#, adv#), byte write enables (bwx#) and global write (gw#). note that ce2# is not available on the t version. asynchronous inputs include the output enable (oe#), clock (clk) and snooze enable (zz). there is also 100-pin tqfp 1 note: 1. jedec-standard ms-026 bha (lqfp). 165-pin fbga (preliminary package data)
2 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance functional block diagram 1 meg x 18 sa0, sa1, sas address register adv# clk binary counter and logic clr q1 q0 adsc# 20 20 18 20 bwb# bwa# ce# byte b write register byte a write register enable register sa0' sa1' oe# sense amps 1 meg x 9 x 2 memory array adsp# 2 sa0-sa1 mode ce2 ce2# gw# bwe# pipelined enable dqs dqpa dqpb 2 output registers input registers e byte b write driver byte a write driver output buffers 9 9 9 9 18 18 18 18 18 note: functional block diagrams illustrate simplified device operation. see truth table, pin descriptions and timing diagrams for detailed information. functional block diagram 512k x 32/36 address register adv# clk binary counter clr q1 q0 adsp# adsc# mode 19 19 17 19 bwd# bwc# bwb# bwa# bwe# gw# ce# ce2 ce2# oe# byte d write register byte c write register byte b write register byte a write register enable register pipelined enable dqs dqpa dqpb dqpc dqpd 4 output registers sense amps 512k x 8 x 4 (x32) 512k x 9 x 4 (x36) memory array output buffers e byte a write driver byte b write driver byte c write driver byte d write driver input registers sa0, sa1, sas sa0' 9 9 9 9 9 9 36 36 36 36 36 9 9 sa1' sa0-sa1
3 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance general description (continued) note: 1. no connect (nc) is used on the x32 version. parity (dqpx) is used on the x36 version. tqfp pin assignment table pin # x18 x32/x36 1 nc nc/ dqpc 1 2nc dqc 3nc dqc 4v dd q 5v ss 6nc dqc 7nc dqc 8 dqb dqc 9 dqb dqc 10 v ss 11 v dd q 12 dqb dqc 13 dqb dqc 14 nc 15 v dd 16 nc 17 v ss 18 dqb dqd 19 dqb dqd 20 v dd q 21 v ss 22 dqb dqd 23 dqb dqd 24 dqpb dqd 25 nc dqd pin # x18 x32/x36 pin # x18 x32/x36 pin # x18 x32/x36 51 nc nc/ dqpa 1 52 nc dqa 53 nc dqa 54 v dd q 55 v ss 56 nc dqa 57 nc dqa 58 dqa 59 dqa 60 v ss 61 v dd q 62 dqa 63 dqa 64 zz 65 v dd 66 nc 67 v ss 68 dqa dqb 69 dqa dqb 70 v dd q 71 v ss 72 dqa dqb 73 dqa dqb 74 dqpa dqb 75 nc dqb 26 v ss 27 v dd q 28 nc dqd 29 nc dqd 30 nc nc/ dqpd 1 31 mode (lbo#) 32 sa 33 sa 34 sa 35 sa 36 sa1 37 sa0 38 dnu 39 dnu 40 v ss 41 v dd 42 sa 43 sa 44 sa 45 sa 46 sa 47 sa 48 sa 49 sa 50 sa a burst mode input (mode) that selects between inter- leaved and linear burst modes. the data-out (q), en- abled by oe#, is also asynchronous. write cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs. burst operation can be initiated with either address status processor (adsp#) or address status controller (adsc#) inputs. subsequent burst addresses can be in- ternally generated as controlled by the burst advance input (adv#). address and write control are registered on-chip to simplify write cycles. this allows self-timed write cycles. individual byte enables allow individual bytes to be written. during write cycles on the x18 device, bwa# controls dqas and dqpa; bwb# controls dqbs and dqpb. during write cycles on the x32 and x36 devices, bwa# controls dqas and dqpa; bwb# controls dqbs and dqpb; bwc# controls dqcs and dqpc; bwd# controls dqds and dqpd. gw# low causes all bytes to be written. parity bits are only available on the x18 and x36 versions. this device incorporates an additional pipelined enable register which delays turning off the output buffer an additional cycle when a deselect is executed. this feature allows depth expansion without penalizing system performance. microns 16mb syncburst srams operate from a +3.3v or +2.5v power supply, and all inputs and outputs are ttl-compatible. users can implement either a 3.3v or 2.5v i/o for the +3.3v v dd or a 2.5v i/o for the +2.5v v dd . the device is ideally suited for pentium ? and powerpc pipelined systems and systems that benefit from a very wide, high-speed data bus. the device is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide applications. please refer to the micron web site ( www.micronsemi.com/en/products/sram/ ) for the lat- est data sheet. 76 v ss 77 v dd q 78 nc dqb 79 nc dqb 80 sa nc/ dqpb 1 81 sa 82 sa 83 adv# 84 adsp# 85 adsc# 86 oe# (g#) 87 bwe# 88 gw# 89 clk 90 v ss 91 v dd 92 ce2# 93 bwa# 94 bwb# 95 nc bwc# 96 nc bwd# 97 ce2 98 ce# 99 sa 100 sa
4 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance pin assignment (top view) 100-pin tqfp note: 1. no connect (nc) is used on the x32 version. parity (dqpx) is used on the x36 version. sa sa adv# adsp# adsc# oe# (g#) bwe# gw# clk v ss v dd ce2# bwa# bwb# nc nc ce2 ce# sa sa 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 sa nc nc v dd q v ss nc dqpa dqa dqa v ss v dd q dqa dqa v ss nc v dd zz dqa dqa v dd q v ss dqa dqa nc nc v ss v dd q nc nc nc sa sa sa sa sa sa sa sa sa v dd v ss dnu dnu sa0 sa1 sa sa sa sa mode (lbo#) nc nc nc v dd q v ss nc nc dqb dqb v ss v dd q dqb dqb nc v dd nc v ss dqb dqb v dd q v ss dqb dqb dqpb nc v ss v dd q nc nc nc x18 sa sa adv# adsp# adsc# oe# (g#) bwe# gw# clk v ss v dd ce2# bwa# bwb# bwc# bwd# ce2 ce# sa sa 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 nc/ dqpb 1 dqb dqb v dd q v ss dqb dqb dqb dqb v ss v dd q dqb dqb v ss nc v dd zz dqa dqa v dd q v ss dqa dqa dqa dqa v ss v dd q dqa dqa nc/ dqpa 1 sa sa sa sa sa sa sa sa sa v dd v ss dnu dnu sa0 sa1 sa sa sa sa mode (lbo#) nc/ dqpc 1 dqc dqc v dd q v ss dqc dqc dqc dqc v ss v dd q dqc dqc nc v dd nc v ss dqd dqd v dd q v ss dqd dqd dqd dqd v ss v dd q dqd dqd nc/ dqpd 1 x32/x36
5 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance tqfp pin descriptions x18 x32/x36 symbol type description 37 37 sa0 input synchronous address inputs: these inputs are registered and must 36 36 sa1 meet the setup and hold times around the rising edge of clk. 32-35, 42-50, 32-35, 42-50, sa 80-82, 99, 81, 82, 99, 100 100 93 93 bwa# input synchronous byte write enables: these active low inputs allow 94 94 bwb# individual bytes to be written and must meet the setup and hold C 95 bwc# times around the rising edge of clk. a byte write enable is low C 96 bwd# for a write cycle and high for a read cycle. for the x18 version, bwa# controls dqa pins and dqpa; bwb# controls dqb pins and dqpb. for the x32 and x36 versions, bwa# controls dqa pins and dqpa; bwb# controls dqb pins and dqpb; bwc# controls dqc pins and dqpc; bwd# controls dqd pins and dqpd. parity is only available on the x18 and x36 versions. 87 87 bwe# input byte write enable: this active low input permits byte write operations and must meet the setup and hold times around the rising edge of clk. 88 88 gw# input global write: this active low input allows a full 18-, 32-, or 36-bit write to occur independent of the bwe# and bwx# lines and must meet the setup and hold times around the rising edge of clk. 89 89 clk input clock: this signal registers the address, data, chip enable, byte write enables and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clocks rising edge. 98 98 ce# input synchronous chip enable: this active low input is used to enable the device and conditions the internal use of adsp#. ce# is sampled only when a new external address is loaded. 92 92 ce2# input synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded. 64 64 zz input snooze enable: this active high, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. when zz is active, all other inputs are ignored. this pin has an internal pull-down and can be floating. 97 97 ce2 input synchronous chip enable: this active high input is used to enable the device and is sampled only when a new external address is loaded. 86 86 oe# input output enable: this active low, asynchronous input enables the (g#) data i/o output drivers. g# is the jedec-standard term for oe#. 83 83 adv# input synchronous address advance: this active low input is used to advance the internal burst counter, controlling burst access after the external address is loaded. a high on this pin effectively causes wait states to be generated (no address advance). to ensure use of correct address during a write cycle, adv# must be high at the rising edge of the first clock after an adsp# cycle is initiated. (continued on next page)
6 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance tqfp pin descriptions (continued) x18 x32/x36 symbol type description 84 84 adsp# input synchronous address status processor: this active low input interrupts any ongoing burst, causing a new external address to be registered. a read is performed using the new address, independent of the byte write enables and adsc#, but dependent upon ce#, ce2, and ce2#. adsp# is ignored if ce# is high. power- down state is entered if ce2 is low or ce2# is high. 85 85 adsc# input synchronous address status controller: this active low input interrupts any ongoing burst, causing a new external address to be registered. a read or write is performed using the new address if ce# is low. adsc# is also used to place the chip into power-down state when ce# is high. 31 31 mode input mode: this input selects the burst sequence. a low on this pin (lbo#) selects linear burst. nc or high on this pin selects interleaved burst. do not alter input state while device is operating. lbo# is the jedec-standard term for mode. (a) 58, 59, (a) 52, 53, dqa input/ sram data i/os: for the x18 version, byte a is associated with 62, 63, 68, 69, 56-59, 62, 63 output dqa pins; byte b is associated with dqb pins. for the x32 and 72, 73 x36 versions, byte a is associated with dqa pins; byte b is (b) 8, 9, 12, (b) 68, 69 dqb associated with dqb pins; byte c is associated with dqc pins; 13, 18, 19, 22, 72-75, 78, 79 byte d is associated with dqd pins. input data must meet setup 23 and hold times around the rising edge of clk. (c) 2, 3, 6-9, dqc 12, 13 (d) 18, 19, dqd 22-25, 28, 29 74 51 nc/ dqpa nc/ no connect/parity data i/os: on the x32 version, these pins are no 24 80 nc/ dqpb i/o connect (nc). on the x18 version, byte a parity is dqpa; byte C 1 nc/ dqpc b parity is dqpb. on the x36 version, byte a parity is dqpa; C 30 nc/ dqpd byte b parity is dqpb; byte c parity is dqpc; byte d parity is dqpd. 15, 41, 65, 15, 41, 65, v dd supply power supply: see dc electrical characteristics and operating 91 91 conditions for range. 4, 11, 20, 27, 4, 11, 20, 27, v dd q supply isolated output buffer supply: see dc electrical characteristics and 54, 61, 70, 77 54, 61, 70, 77 operating conditions for range. 5, 10, 17, 21, 5, 10, 17, 21, v ss supply ground: gnd. 26, 40, 55, 60, 26, 40, 55, 60, 67, 71, 76, 90 67, 71, 76, 90 38, 39 38, 39 dnu C do not use: these signals may either be unconnected or wired to gnd to improve package heat dissipation. 1-3, 6, 7, 14 14, 16, 66 nc C no connect: these signals are not internally connected and may be 16, 25, 28-30, connected to ground to improve package heat dissipation. 51-53, 56, 57, 66, 75, 78, 79, 95, 96 na na nf C no function: these pins are internally connected to the die and have the capacitance of an input pin. it is allowable to leave these pins unconnected or driven by signals.
7 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance pin layout (top view) 165-pin fbga a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 2 ce# ce2 v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc dqb dqb dqb dqb v ss nc nc nc nc nc nc nc nc nc nc nc nc nc nc v dd dqb dqb dqb dqb dqpb nc mode (lbo#) bwb# nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa nc bwa# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss nc dnu dnu ce2# clk v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss sa sa1 sa0 bwe# gw# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss dnu dnu adsc# oe# (g#) v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa adv# adsp# v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc nc nc nc nc nc dqa dqa dqa dqa nc sa sa sa nc dqpa dqa dqa dqa dqa zz nc nc nc nc nc sa sa top view 3456789 10 11 1 a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 2 ce# ce2 v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc dqc dqc dqc dqc v ss dqd dqd dqd dqd nc nc nc nc nc nc/ dqpc dqc dqc dqc dqc v dd dqd dqd dqd dqd nc/ dqpd nc mode (lbo#) bwc# bwd# v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa bwb# bwa# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss nc dnu dnu ce2# clk v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss sa sa1 sa0 bwe# gw# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss dnu dnu adsc# oe# (g#) v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa adv# adsp# v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc dqb dqb dqb dqb nc dqa dqa dqa dqa nc sa sa nc nc nc/ dqpb dqb dqb dqb dqb zz dqa dqa dqa dqa nc/ dqpa sa sa top view 3456789 10 11 1 x18 x32/x36 *no connect (nc) is used on the x32 version. parity (dqpx) is used on the x36 version.
8 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance fbga pin descriptions x18 x32/x36 symbol type description 6r 6r sa0 input synchronous address inputs: these inputs are registered and must 6p 6p sa1 meet the setup and hold times around the rising edge of clk. 2a, 2b, 3p, 2a, 2b, 3p, sa 3r, 4p, 4r, 6n, 3r, 4p, 4r, 6n, 8p, 8r, 9p, 9r, 8p, 8r, 9p, 10a, 10b, 10p, 9r, 10a, 10b, 10r, 11a, 11p, 10p, 10r, 11p, 11r 11r 5b 5b bwa# input synchronous byte write enables: these active low inputs allow 4a 5a bwb# indivi dual bytes to be written and must meet the setup and hold C 4a bwc# times around the rising edge of clk. a byte write enable is low C 4b bwd# for a write cycle and high for a read cycle. for the x18 version, bwa# controls dqas and dqpa; bwb# controls dqbs and dqpb. for the x32 and x36 versions, bwa# controls dqas and dqpa; bwb# controls dqbs and dqpb; bwc# controls dqcs and dqpc; bwd# controls dqds and dqpd. parity is only available on the x18 and x36 versions. 7a 7a bwe# input byte w rite enable: this active low input permits byte write operations and must meet the setup and hold times around the rising edge of clk. 7b 7b gw# input g lobal write: this active low input allows a full 18-, 32- or 36-bit write to occur independent of the bwe# and bwx# lines and must meet the setup and hold times around the rising edge of clk. 6b 6b clk input clock: this signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clocks rising edge. 3a 3a ce# input synchronous chip enable: this active low input is used to enable the device and conditions the internal use of adsp#. ce# is sampled only when a new external address is loaded. 6a 6a ce2# input synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded. 11h 11h zz input snooze enable: this active high, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. when zz is active, all other inputs are ignored. 3b 3b ce2 input synchronous chip enable: this active high input is used to enable the device and is sampled only when a new external address is loaded. 8b 8b oe#(g#) input output enable: this active low, asynchronous input enables the data i/o output drivers. (continued on next page)
9 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance fbga pin descriptions (continued) x18 x32/x36 symbol type description 9a 9a adv# input synchronous address advance: this active low input is used to advance the internal burst counter, controlling burst access after the external address is loaded. a high on adv# effectively causes wait states to be generated (no address advance). to ensure use of correct address during a write cycle, adv# must be high at the rising edge of the first clock after an adsp# cycle is initiated. 9b 9b adsp# input synchronous address status processor: this active low input interrupts any ongoing burst, causing a new external address to be registered. a read is performed using the new address, independent of the byte write enables and adsc#, but dependent upon ce#, ce2, and ce2#. adsp# is ignored if ce# is high. power- down state is entered if ce2 is low or ce2# is high. 8a 8a adsc# input synchronous address status controller: this active low input interrupts any ongoing burst, causing a new external address to be registered. a read or write is performed using the new address if ce# is low. adsc# is also used to place the chip into power-down state when ce# is high. 1r 1r mode input mode: this input selects the burst sequence. a low on this (lb0#) input selects linear burst. nc or high on this input selects interleaved burst. do not alter input state while device is operating. (a) 10j, 10k, (a) 10j, 10k, dqa input/ sram data i/os: for the x18 version, byte a is associated dqas; 10l, 10m, 11d, 10l, 10m, 11j, output byte b is associated with dqbs. for the x32 and x36 versions, 11e, 11f, 11g 11k, 11l, 11m byte a is associated with dqas; byte b is associated with dqbs; (b) 1j, 1k, (b) 10d, 10e, dqb byte c is associated with dqcs; byte d is associated with dqds. 1l, 1m, 2d, 10f, 10g, 11d, input data must meet setup and hold times around the rising edge 2e, 2f, 2g 11e, 11f, 11g of clk. (c) 1d, 1e, dqc 1f, 1g, 2d, 2e, 2f, 2g (d) 1j, 1k, 1l, dqd 1m, 2j, 2k, 2l, 2m 11c 11n nc/ dqpa nc/ no connect/parity data i/os: on the x32 version, these are no 1n 11c nc/ dqpb i/o connect (nc). on the x18 version, byte a parity is dqpa; byte b C 1c nc/ dqpc parity is dqpb. on the x36 version, byte a parity is dqpa; byte C 1n nc/ dqpd b parity is dqpb; byte c parity is dqpc; byte d parity is dqpd. 1h, 4d, 4e, 4f, 1h, 4d, 4e, 4f, v dd supply power supply: see dc electrical characteristics and operating 4g, 4h, 4j, 4g, 4h, 4j, conditions for range. 4k, 4l, 4m, 4k, 4l, 4m, 8d, 8e, 8f, 8d, 8e, 8f, 8g, 8h, 8j, 8g, 8h, 8j, 8k, 8l, 8m 8k, 8l, 8m (continued on next page)
10 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance fbga pin descriptions (continued) x18 x32/x36 symbol type description 3c, 3d, 3e, 3c, 3d, 3e, v dd q supply isolated output buffer supply: see dc electrical characteristics and 3f, 3g, 3j, 3f, 3g, 3j, operating conditions for range. 3k, 3l, 3m, 3k, 3l, 3m, 3n, 9c, 9d, 3n, 9c, 9d, 9e, 9f, 9g, 9e, 9f, 9g, 9j, 9k, 9l, 9j, 9k, 9l, 9m, 9n 9m, 9n 2h, 4c, 4n, 5c, 2h, 4c, 4n, 5c, v ss supply ground: gnd. 5d, 5e 5f, 5d, 5e 5f, 5g, 5h, 5j, 5g, 5h, 5j, 5k, 5l, 5m, 5k, 5l, 5m, 6c, 6d, 6e, 6f, 6c, 6d, 6e, 6f, 6g, 6h, 6j, 6g, 6h, 6j, 6k, 6l, 6m, 6k, 6l, 6m, 7c, 7d, 7e, 7c, 7d, 7e, 7f, 7g, 7h, 7f, 7g, 7h, 7j, 7k, 7l, 7j, 7k, 7l, 7m, 7n, 8c, 8n 7m, 7n, 8c, 8n 5p, 5r, 7p, 7r 5p, 5r, 7p, 7r dnu C do not use: these signals may either be unconnected or wired to gnd to improve package heat dissipation. 1a, 1b, 1c, 1a, 1b, 1p, nc C no connect: these signals are not internally connected and 1d, 1e, 1f, 2c, 2n, 2p, may be connected to ground to improve package heat 1g, 1p, 2c, 2r, 3h, 5n, dissipation. 2j, 2k, 2l, 9h, 10c, 10h, 2m, 2n, 2p, 10n, 11a, 11b 2r, 3h, 4b, 5a, 5n, 9h, 10c, 10d, 10e, 10f, 10g, 10h, 10n, 11b, 11j, 11k, 11l, 11m, 11n
11 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance interleaved burst address table (mode = nc or high) first address (external) second address (internal) third address (internal) fourth address (internal) x...x00 x...x01 x...x10 x...x11 x...x01 x...x00 x...x11 x...x10 x...x10 x...x11 x...x00 x...x01 x...x11 x...x10 x...x01 x...x00 linear burst address table (mode = low) first address (external) second address (internal) third address (internal) fourth address (internal) x...x00 x...x01 x...x10 x...x11 x...x01 x...x10 x...x11 x...x00 x...x10 x...x11 x...x00 x...x01 x...x11 x...x00 x...x01 x...x10 partial truth table for write commands (x18) function gw# bwe# bwa# bwb# read h h x x read h l h h write byte a h l l h write byte b h l h l write all bytes h l l l write all bytes l x x x partial truth table for write commands (x32/x36) function gw# bwe# bwa# bwb# bwc# bwd# read h h x x x x read h l h h h h write byte a h l l h h h write all bytes h l l l l l write all bytes l x x x x x note: using bwe# and bwa# through bwd#, any one or more bytes may be written.
12 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance truth table (notes 1-8) address operation used ce# ce2# ce2 zz adsp# adsc# adv# write# oe# clk dq deselect cycle, power-down none h x x l x l x x x l-h high-z deselect cycle, power-down none l x l l l x x x x l-h high-z deselect cycle, power-down none l h x l l x x x x l-h high-z deselect cycle, power-down none l x l l h l x x x l-h high-z deselect cycle, power-down none l h x l h l x x x l-h high-z snooze mode, power-down none x x x h xxxxx x high-z read cycle, begin burst external l l h l l x x x l l-h q read cycle, begin burst external l l h l l x x x h l-h high-z write cycle, begin burst external l l h l h l x l x l-h d read cycle, begin burst external l l h l h l x h l l-h q read cycle, begin burst external l l h l h l x h h l-h high-z read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h high-z read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h high-z write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l hhhhll-hq read cycle, suspend burst current x x x l hhhhhl-h high-z read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h high-z write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d note: 1. x means dont care. # means active low. h means logic high. l means logic low. 2. for write#, l means any one or more byte write enable signals (bwa#, bwb#, bwc# or bwd#) and bwe# are low or gw# is low. write# = h for all bwx#, bwe#, gw# high. 3. bwa# enables writes to dqas and dqpa. bwb# enables writes to dqbs and dqpb. bwc# enables writes to dqcs and dqpc. bwd# enables writes to dqds and dqpd. dqpa and dqpb are only available on the x18 and x36 versions. dqpc and dqpd are only available on the x36 version. 4. all inputs except oe# and zz must meet setup and hold times around the rising edge (low to high) of clk. 5. wait states are inserted by suspending burst. 6. for a write operation following a read operation, oe# must be high before the input data setup time and held high throughout the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 8. adsp# low always initiates an internal read at the l-h edge of clk. a write is performed by setting one or more byte write enable signals and bwe# low or gw# low for the subsequent l-h edge of clk. refer to write timing diagram for clarification.
13 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance 3.3v v dd , absolute maximum ratings* voltage on v dd supply relative to v ss ................................ -0.5v to +4.6v voltage on v dd q supply relative to v ss ................................ -0.5v to +4.6v v in (dqx) .................................... -0.5v to v dd q + 0.5v v in (inputs) ................................... -0.5v to v dd + 0.5v storage temperature (tqfp) .............. -55oc to +150oc storage temperature (fbga) .............. -55oc to +125oc junction temperature** ................................... +150oc short circuit output current ............................ 100ma 2.5v v dd , absolute maximum ratings* voltage on v dd supply relative to v ss ................................ -0.3v to +3.6v voltage on v dd q supply relative to v ss ................................ -0.3v to +3.6v v in (dqx) .................................... -0.3v to v dd q + 0.3v v in (inputs) ................................... -0.3v to v dd + 0.3v storage temperature (tqfp) .............. -55oc to +150oc storage temperature (fbga) .............. -55oc to +125oc junction temperature** ................................... +150oc short circuit output current ............................ 100ma *stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only, and functional opera- tion of the device at these or any other conditions above those indicated in the operational sections of this speci- fication is not implied. exposure to absolute maximum rating conditions for extended periods may affect reli- ability. **maximum junction temperature depends upon pack- age type, cycle time, loading, ambient temperature and airflow. see micron technical note tn-05-14 for more information. 3.3v v dd , 3.3v i/o dc electrical characteristics and operating conditions (0oc t a +70oc; v dd = +3.3v 0.165v; v dd q = +3.3v 0.165v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage v ih 2.0 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.8 v 1, 2 input leakage current 0v v in v dd il i -1.0 1.0 a 3 output leakage current output(s) disabled, il o -1.0 1.0 a 0v v in v dd output high voltage i oh = -4.0ma v oh 2.4 C v 1, 4 output low voltage i ol = 8.0ma v ol C 0.4 v 1, 4 supply voltage v dd 3.135 3.465 v 1 isolated output buffer supply v dd q 3.135 3.465 v 1, 5 note: 1. all voltages referenced to v ss (gnd). 2. for 3.3v v dd : overshoot: v ih +4.6v for t t kc/2 for i 20ma undershoot: v il 3 -0.7v for t t kc/2 for i 20ma power-up: v ih +3.6v and v dd 3.135v for t 200ms for 2.5v v dd : overshoot: v ih +3.6v for t t kc/2 for i 20ma undershoot: v il 3 -0.5v for t t kc/2 for i 20ma power-up: v ih +2.65v and v dd 2.375v for t 200ms 3. mode has an internal pull-up, and input leakage = 10a. 4. the load used for v oh , v ol testing is shown in figure 2. ac load current is higher than the stated dc values. ac i/o curves are available upon request. 5. v dd q should never exceed v dd . v dd and v dd q can be connected together.
14 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance 3.3v v dd , 2.5v i/o dc electrical characteristics and operating conditions (0oc t a +70oc; v dd = +3.3v 0.165v; v dd q = +2.5v 0.125v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage data bus (dqx) v ih q 1.7 v dd q + 0.3 v 1, 2 inputs v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -1.0 1.0 a 3 output leakage current output(s) disabled, il o -1.0 1.0 a 0v v in v dd q (dqx) output high voltage i oh = -2.0ma v oh 1.7 C v 1, 4 i oh = -1.0ma v oh 2.0 C v 1, 4 output low voltage i ol = 2.0ma v ol C 0.7 v 1, 4 i ol = 1.0ma v ol C 0.4 v 1, 4 supply voltage v dd 3.135 3.6 v 1 isolated output buffer supply v dd q 2.375 2.625 v 1 2.5v v dd , 2.5v i/o dc electrical characteristics and operating conditions (0oc t a +70oc; v dd = +2.5v 0.125v; v dd q = +2.5v 0.125v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage data bus (dqx) v ih q 1.7 v dd q + 0.3 v 1, 2 inputs v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -1.0 1.0 a 3 output leakage current output(s) disabled, il o -1.0 1.0 a 0v v in v dd q (dqx) output high voltage i oh = -2.0ma v oh 1.7 C v 1, 4 i oh = -1.0ma v oh 2.0 C v 1, 4 output low voltage i ol = 2.0ma v ol C 0.7 v 1, 4 i ol = 1.0ma v ol C 0.4 v 1, 4 supply voltage v dd 2.375 2.625 v 1 isolated output buffer supply v dd q 2.375 2.625 v 1 note: 1. all voltages referenced to v ss (gnd). 2. for 3.3v v dd : overshoot: v ih +4.6v for t t kc/2 for i 20ma undershoot: v il 3 -0.7v for t t kc/2 for i 20ma power-up: v ih +3.6v and v dd 3.135v for t 200ms for 2.5v v dd : overshoot: v ih +3.6v for t t kc/2 for i 20ma undershoot: v il 3 -0.5v for t t kc/2 for i 20ma power-up: v ih +2.65v and v dd 2.375v for t 200ms 3. mode has an internal pull-up, and input leakage = 10a. 4. the load used for v oh , v ol testing is shown in figure 4 for 2.5v i/o. ac load current is higher than the shown dc values. ac i/o curves are available upon request. 5. this parameter is sampled.
15 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance tqfp thermal resistance description conditions symbol typ units notes thermal resistance test conditions follow standard test methods q ja 46 oc/w 1 (junction to ambient) and procedures for measuring thermal thermal resistance impedance, per eia/jesd51. q jc 2.8 oc/w 1 (junction to top of case) note: 1. this parameter is sampled. tqfp capacitance description conditions symbol typ max units notes control input capacitance t a = 25oc; f = 1 mhz; c i 34pf1 input/output capacitance (dq) v dd = 3.3v c o 45pf1 address capacitance c a 3 3.5 pf 1 clock capacitance c ck 3 3.5 pf 1 fbga thermal resistance description conditions symbol typ units notes junction to ambient test conditions follow standard test methods q ja 40 oc/w 1 (airflow of 1m/s) and procedures for measuring thermal junction to case (top) impedance, per eia/jesd51. q jc 9 oc/w 1 junction to pins q jb 17 oc/w 1 (bottom) fbga capacitance description conditions symbol typ max units notes address/control input capacitance c i 2.5 3.5 pf 1 output capacitance (q) t a = 25oc; f = 1 mhz c o 45pf1 clock capacitance c ck 2.5 3.5 pf 1
16 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance note: 1. if v dd = +3.3v, then v dd q = +3.3v or +2.5v. if v dd = +2.5v, then v dd q = +2.5v. voltage tolerances: +3.3v 0.165 or +2.5v 0.125v for all values of v dd and v dd q. 2. i dd is specified with no output current and increases with faster cycle times. i dd q increases with faster cycle times and greater output loading. 3. device deselected means device is in power-down mode as defined in the truth table. device selected means device is active (not in power-down mode). 4. typical values are measured at 3.3v, 25oc, and 10ns cycle time. i dd operating conditions and maximum limits (note 1, unless otherwise noted)(0oc t a +70oc) description conditions symbol typ -6 -7.5 -10 units notes power supply device selected; all inputs v il current: or 3 v ih ; cycle time 3 t kc (min); i dd 225 475 425 325 ma 2, 3, 4 operating v dd = max; outputs open power supply device selected; v dd = max; current: idle adsc#, adsp#, gw#, bwx#, adv# 3 i dd 1 55 110 100 85 ma 2, 3, 4 v ih ; all inputs v ss + 0.2 or 3 v dd - 0.2; cycle time 3 t kc (min) cmos standby device deselected; v dd = max; all inputs v ss + 0.2 or 3 v dd - 0.2; i sb 2 0.4 10 10 10 ma 3, 4 all inputs static; clk frequency = 0 ttl standby device deselected; v dd = max; all inputs v il or 3 v ih ;i sb 3 8 252525ma3, 4 all inputs static; clk frequency = 0 clock running device deselected; v dd = max; adsc#, adsp#, gw#, bwx#, adv# 3 i sb 4 55 110 90 85 ma 3, 4 v ih ; all inputs v ss + 0.2 or 3 v dd - 0.2; cycle time 3 t kc (min) max
17 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance note: 1. test conditions as specified with the output loading shown in figure 1 for +3.3v i/o (v dd q = +3.3v 0.165v) and figure 3 for 2.5v i/o (v dd q = +2.5v 0.125v) unless otherwise noted. 2. measured as high above v ih and low below v il . 3. this parameter is measured with the output loading shown in figure 2. 4. this parameter is sampled. 5. transition is measured 500mv from steady state voltage. 6. refer to technical note tn-58-09, synchronous sram bus contention design considerations, for a more thorough discussion on these parameters. 7. oe# is a dont care when a byte write enable is sampled low. 8. a write cycle is defined by at least one byte write enable low and adsp# high for the required setup and hold times. a read cycle is defined by all byte write enables high and adsc# or adv# low or adsp# low for the required setup and hold times. 9. this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clk when either adsp# or adsc# is low and chip enabled. all other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (clk) when the chip is enabled. chip enable must be valid at each rising edge of clk when either adsp# or adsc# is low to remain enabled. 10. if v dd = +3.3v, then v dd q = +3.3v or +2.5v. if v dd = +2.5v, then v dd q = +2.5v. voltage tolerances: +3.3v 0.165 or +2.5v 0.125v for all values of v dd and v dd q. ac electrical characteristics and recommended operating conditions (notes 1, 10 unless otherwise noted) (0oc t a +70oc) -6 -7.5 -10 description symbol min max min max min max units notes clock clock cycle time t kc 6.0 7.5 10 ns clock frequency f kf 166 133 100 mhz clock high time t kh 2.3 2.5 3.0 ns 2 clock low time t kl 2.3 2.5 3.0 ns 2 output times clock to output valid t kq 3.5 4.0 5.0 ns clock to output invalid t kqx 1.5 1.5 1.5 ns 3 clock to output in low-z t kqlz 0 0 0 ns 3, 4, 5, 6 clock to output in high-z t kqhz 3.5 4.2 5.0 ns 3, 4, 5, 6 oe# to output valid t oeq 3.5 4.2 5.0 ns 7 oe# to output in low-z t oelz 0 0 0 ns 3, 4, 5, 6 oe# to output in high-z t oehz 3.5 4.2 4.5 ns 3, 4, 5, 6 setup times address t as 1.5 1.5 2.0 ns 8, 9 address status (adsc#, adsp#) t adss 1.5 1.5 2.0 ns 8, 9 address advance (adv#) t aas 1.5 1.5 2.0 ns 8, 9 write signals t ws 1.5 1.5 2.0 ns 8, 9 (bwa#-bwd#, bwe#, gw#) data-in t ds 1.5 1.5 2.0 ns 8, 9 chip enables (ce#, ce2#, ce2) t ces 1.5 1.5 2.0 ns 8, 9 hold times address t ah 0.5 0.5 0.5 ns 8, 9 address status (adsc#, adsp#) t adsh 0.5 0.5 0.5 ns 8, 9 address advance (adv#) t aah 0.5 0.5 0.5 ns 8, 9 write signals t wh 0.5 0.5 0.5 ns 8, 9 (bwa#-bwd#, bwe#, gw#) data-in t dh 0.5 0.5 0.5 ns 8, 9 chip enables (ce#, ce2#, ce2) t ceh 0.5 0.5 0.5 ns 8, 9
18 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance q 50 v = 1.5v z = 50 o t figure 1 q 351 317 5pf +3.3v figure 2 3.3v v dd , 3.3v i/o ac test conditions input pulse levels ................... v ih = (v dd /2.2) + 1.5v .................... v il = (v dd /2.2) - 1.5v input rise and fall times ...................................... 1ns input timing reference levels ....................... v dd /2.2 output reference levels ............................. v dd q/2.2 output load .............................. see figures 1 and 2 load derating curves micron 1 meg x 18, 512k x 32 and 512k x 36 syncburst sram timing is dependent upon the capaci- tive loading on the outputs. consult the factory for copies of i/o current versus voltage curves. 3.3v i/o output load equivalents 3.3v v dd , 2.5v i/o ac test conditions input pulse levels ............... v ih = (v dd /2.64) + 1.25v ................ v il = (v dd /2.64) - 1.25v input rise and fall times ...................................... 1ns input timing reference levels ..................... v dd /2.64 output reference levels ................................ v dd q/2 output load .............................. see figures 3 and 4 2.5v v dd , 2.5v i/o ac test conditions input pulse levels .................... v ih = (v dd /2) + 1.25v ..................... v il = (v dd /2) - 1.25v input rise and fall times ...................................... 1ns input timing reference levels .......................... v dd /2 output reference levels ................................ v dd q/2 output load .............................. see figures 3 and 4 q 50 w v = 1.25v z = 50 w o t figure 3 q 351 317 5pf +3.3v figure 4 2.5v i/o output load equivalents
19 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance snooze mode snooze mode is a low-current, power-down mode in which the device is deselected and current is reduced to i sb 2 z . the duration of snooze mode is dictated by the length of time zz is in a high state. after the device enters snooze mode, all inputs except zz become gated inputs and are ignored. zz is an asynchronous, active high input that causes the device to enter snooze mode. when zz becomes a logic high, i sb 2 z is guaranteed after the setup time t zz is met. any read or write operation pending when the device enters snooze mode is not guaranteed to complete successfully. therefore, snooze mode must not be initiated until valid pending operations are completed. snooze mode electrical characteristics description conditions symbol min max units notes current during snooze mode zz 3 v ih i sb 2z 10 ma zz active to input ignored t zz 2( t kc) ns 1 zz inactive to input sampled t rzz 2( t kc) ns 1 zz active to snooze current t zzi 2( t kc) ns 1 zz inactive to exit snooze current t rzzi 0 ns 1 note: 1. this parameter is sampled. snooze mode waveform t zz i supply clk zz t rzz all inputs (except zz) dont care i isb2z t zzi t rzzi outputs (q) high-z deselect or read only
20 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance read timing 3 t kc t kl clk adsp# t adsh t adss address t kh oe# adsc# ce# (note 2) t ah t as a1 t ceh t ces gw#, bwe#, bwa#-bwd# q high-z t kqlz t kqx t kq adv# t oehz t kq single read burst read t oeq t oelz t kqhz burst wraps around to its initial state. t aah t aas t wh t ws t adsh t adss q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a3) q(a2 + 3) a2 a3 (note 1) deselect cycle. (note 3) burst continued with new base address. (note 4) adv# suspends burst. dont care undefined note: 1. q(a2) refers to output from address a2. q(a2 + 1) refers to output from the next internal burst address following a2. 2. ce2# and ce2 have timing identical to ce#. on this diagram, when ce# is low, ce2# is low and ce2 is high. when ce# is high, ce2# is high and ce2 is low. 3. timing is shown assuming that the device was not enabled before entering into this sequence. oe# does not cause q to be driven until after the following clock rising edge. 4. outputs are disabled within two clock cycles after deselect. -6 -7.5 -10 sym min max min max min max units t as 1.5 1.5 2.0 ns t adss 1.5 1.5 2.0 ns t aas 1.5 1.5 2.0 ns t ws 1.5 1.5 2.0 ns t ces 1.5 1.5 2.0 ns t ah 0.5 0.5 0.5 ns t adsh 0.5 0.5 0.5 ns t aah 0.5 0.5 0.5 ns t wh 0.5 0.5 0.5 ns t ceh 0.5 0.5 0.5 ns read timing parameters -6 -7.5 -10 sym min max min max min max units t kc 6.0 7.5 10 ns f kf 166 133 100 mhz t kh 2.3 2.5 3.0 ns t kl 2.3 2.5 3.0 ns t kq 3.5 4.0 5.0 ns t kqx 1.5 1.5 1.5 ns t kqlz 0 0 1.0 ns t kqhz 3.5 4.2 5.0 ns t oeq 3.5 4.2 5.0 ns t oelz 0 0 0 ns t oehz 3.5 4.2 4.5 ns
21 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance write timing t kc t kl clk adsp# t adsh t adss address t kh oe# adsc# ce# (note 2) t ah t as a1 t ceh t ces bwe#, bwa#-bwd# q high-z adv# burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 d extended burst write d(a2 + 2) single write t adsh t adss t adsh t adss t oehz t aah t aas t wh t ws t dh t ds (note 3) (note 1) (note 4) gw# t wh t ws (note 5) byte write signals are ignored for first cycle when adsp# initiates burst. adsc# extends burst. adv# suspends burst. dont care undefined d(a1) note: 1. d(a2) refers to input for address a2. d(a2 + 1) refers to input for the next internal burst address following a2. 2. ce2# and ce2 have timing identical to ce#. on this diagram, when ce# is low, ce2# is low and ce2 is high. when ce# is high, ce2# is high and ce2 is low. 3. oe# must be high before the input data setup and held high throughout the data hold time. this prevents input/ output data contention for the time period prior to the byte write enable inputs being sampled. 4. adv# must be high to permit a write to the loaded address. 5. full-width write can be initiated by gw# low; or by gw# high, bwe# low and bwa#-bwb# low for x18 device; or gw# high, bwe# low and bwa#-bwd# low for x32 and x36 devices. -6 -7.5 -10 sym min max min max min max units t ds 1.5 1.5 2.0 ns t ces 1.5 1.5 2.0 ns t ah 0.5 0.5 0.5 ns t adsh 0.5 0.5 0.5 ns t aah 0.5 0.5 0.5 ns t wh 0.5 0.5 0.5 ns t dh 0.5 0.5 0.5 ns t ceh 0.5 0.5 0.5 ns write timing parameters -6 -7.5 -10 sym min max min max min max units t kc 6.0 7.5 10 ns f kf 166 133 100 mhz t kh 2.3 2.5 3.0 ns t kl 2.3 2.5 3.0 ns t oehz 3.5 4.2 4.5 ns t as 1.5 1.5 2.0 ns t adss 1.5 1.5 2.0 ns t aas 1.5 1.5 2.0 ns t ws 1.5 1.5 2.0 ns
22 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance read/write timing 3 t kc t kl clk adsp# t adsh t adss address t kh oe# adsc# ce# (note 2) t ah t as a2 t ceh t ces q high-z adv# single write d(a3) a4 a5 a6 d(a5) d(a6) d burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t wh t ws q(a4+3) t oehz t dh t ds t oelz (note 5) t kqlz t kq back-to-back writes a1 bwe#, bwa#-bwd# (note 4) a3 dont care undefined note: 1. q(a4) refers to output from address a4. q(a4 + 1) refers to output from the next internal burst address following a4. 2. ce2# and ce2 have timing identical to ce#. on this diagram, when ce# is low, ce2# is low and ce2 is high. when ce# is high, ce2# is high and ce2 is low. 3. the data bus (q) remains in high-z following a write cycle unless an adsp#, adsc# or adv# cycle is performed. 4. gw# is high. 5. back-to-back reads may be controlled by either adsp# or adsc#. -6 -7.5 -10 sym min max min max min max units t adss 1.5 1.5 2.0 ns t ws 1.5 1.5 2.0 ns t ds 1.5 1.5 2.0 ns t ces 1.5 1.5 2.0 ns t ah 0.5 0.5 0.5 ns t adsh 0.5 0.5 0.5 ns t wh 0.5 0.5 0.5 ns t dh 0.5 0.5 0.5 ns t ceh 0.5 0.5 0.5 ns read/write timing parameters -6 -7.5 -10 sym min max min max min max units t kc 6.0 7.5 10 ns f kf 166 133 100 mhz t kh 2.3 2.5 3.0 ns t kl 2.3 2.5 3.0 ns t kq 3.5 4.0 5.0 ns t kqlz 0 0 1.0 ns t oelz 0 0 0 ns t oehz 3.5 4.2 4.5 ns t as 1.5 1.5 2.0 ns
23 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance ieee 1149.1 serial boundary scan (jtag) the sram incorporates a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are excluded be- cause their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standard 2.5v i/o logic levels. the sram contains a tap controller, instruction register, boundary scan register, bypass register and id register. disabling the jtag feature these pins can be left floating (unconnected), if the jtag function is not to be implemented. upon power- up, the device will come up in a reset state which will not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see figure 5. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) of any register. (see figure 6.) figure 5 tap controller state diagram note: the 0/1 next to each state represents the value of tms at the rising edge of tck. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0
24 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine. (see figure 5.) the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any regis- ter. (see figure 6.) performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in figure 5. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board- level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for 9mb and 18mb claymore srams. the x36 configuration has a 68-bit-long register, and the x18 configuration has a 49-bit-long register. the boundary scan register is loaded with the con- tents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift- dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register* 0 1 2 . . x . . . selection circuitry selection circuitry tck tms tap controller tdi tdo *x = 49 for the x18 configuration, x = 68 for the x36 configuration. figure 6 tap controller block diagram
25 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32- bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction codes table. three of these instruc- tions are listed as reserved and should not be used. the other five instructions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully imple- mented. the tap controller cannot be used to load address, data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather it performs a capture of the i/o ring when these instruc- tions are executed. instructions are loaded into the tap controller dur- ing the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instruc- tions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. extest is not implemented in this sram tap controller, and therefore this device is not compli- ant to 1149.1. the tap controller does recognize an all-0 instruc- tion. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/ preload instruction has been loaded. there is one difference between the two instructions. unlike the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the in- struction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruc- tion. the preload portion of this instruction is not implemented, so the device tap controller is not fully 1149.1-compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bi-directional pins is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be cap- tured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controllers capture setup plus hold time ( t cs plus t ch). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command.
26 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance bypass when the bypass instruction is loaded in the in- struction register and the tap is placed in a shift-dr state, the bypass register is placed between tdi and tdo. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instruction are not implemented but are re- served for future use. do not use these instructions. t tlth test clock (tck) 123456 test mode select (tms) t thtl test data-out (tdo) t thth test data-in (tdi) t thmx t mvth t thdx t dvth t tlox t tlov dont care undefined tap timing tap ac electrical characteristics (notes 1, 2) (+20oc t j +100oc; +2.4v v dd +2.6v) description symbol min max units clock clock cycle time t thth 100 ns clock frequency f tf 10 mhz clock high time t thtl 40 ns clock low time t tlth 40 ns output times tck low to tdo unknown t tlox 0 ns tck low to tdo valid t tlov 20 ns tdi valid to tck high t dvth 10 ns tck high to tdi invalid t thdx 10 ns setup times tms setup t mvth 10 ns capture setup t cs 10 ns hold times tms hold t thmx 10 ns capture hold t ch 10 ns note: 1. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 2. test conditions are specified using the load in figure 7.
27 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance tap ac test conditions input pulse levels ....................................... v ss to 2.5v input rise and fall times ......................................... 1ns input timing reference levels ............................. 1.25v output reference levels ..................................... 1.25v test load termination supply voltage ............... 1.25v tdo 1.25v 20pf z = 50 w o 50 w figure 7 tap ac output load equivalent tap dc electrical characteristics and operating conditions (+20oc t j +110oc; +2.4v v dd +2.6v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -5.0 5.0 a output leakage current output(s) disabled, il o -5.0 5.0 a 0v v in v dd q (dqx) output low voltage i olc = 100a v ol 1 0.2 v 1 output low voltage i olt = 2ma v ol 2 0.7 v 1 output high voltage i ohc = -100a v oh 1 2.1 v 1 output high voltage i oht = -2ma v oh 2 1.7 v 1 note: 1. all voltages referenced to v ss (gnd). 2. overshoot: v ih (ac) v dd + 1.5v for t t khkh/2 undershoot: v il (ac) 3 -0.5v for t t khkh/2 power-up: v ih +2.6v and v dd 2.4v and v dd q 1.4v for t 200ms during normal operation, v dd q must not exceed v dd . control input signals (such as ld#, r/w#, etc.) may not have pulse widths less than t khkl (min) or operate at frequencies exceeding f kf (max).
28 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance identification register definitions instruction field 512k x 18 description revision number xxxx reserved for version number. (31:28) device depth 00111 defines depth of 256k or 512k words. (27:23) device width 00011 defines width of x18 or x36 bits. (22:18) micron device id xxxxxx reserved for future use. (17:12) micron jedec id 00000101100 allows unique identification of sram vendor. code (11:1) id register presence 1 indicates the presence of an id register. indicator (0) scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 68 instruction codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations.
29 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance fbga boundary scan order (x18) fbga bit# signal name pin id fbga bit# signal name pin id 1 sa tbd 2 sa tbd 3 sa tbd 4 sa tbd 5 sa tbd 6 sa tbd 7 sa tbd 8 dqa tbd 9 dqa tbd 10 dqa tbd 11 dqa tbd 12 zz tbd 13 dqa tbd 14 dqa tbd 15 dqa tbd 16 dqa tbd 17 dqpa tbd 18 sa tbd 19 sa tbd 20 sa tbd 21 adv# tbd 22 adsp tbd 23 adsc# tbd 24 oe# (g#) tbd 25 bwe# tbd 26 gw# tbd 27 clk tbd 28 sa tbd 29 bwa# tbd 30 bwb# tbd 31 sa tbd 32 ce# tbd 33 sa tbd 34 sa tbd 35 dqb tbd 36 dqb tbd 37 dqb tbd 38 dqb tbd 39 v dd tbd 40 dqb tbd 41 dqb tbd 42 dqb tbd 43 dqb tbd 44 dqpb tbd 45 mode (lbo#) tbd 46 sa tbd 47 sa tbd 48 sa tbd 49 sa tbd 50 sa1 tbd 51 sa0 tbd
30 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance fbga boundary scan order (x32/36) 36 sa tbd 37 bwa# tbd 38 bwb# tbd 39 bwc# tbd 40 bwd# tbd 41 sa tbd 42 ce# tbd 43 sa tbd 44 sa tbd 45 nc/ dqpc tbd 46 dqc tbd 47 dqc tbd 48 dqc tbd 49 dqc tbd 50 dqc tbd 51 dqc tbd 52 dqc tbd 53 dqc tbd 54 v dd tbd 55 dqd tbd 56 dqd tbd 57 dqd tbd 58 dqd tbd 59 dqd tbd 60 dqd tbd 61 dqd tbd 62 dqd tbd 63 nc/ dqpd tbd 64 mode (lbo#) tbd 65 sa tbd 66 sa tbd 67 sa tbd 68 sa tbd 69 sa1 tbd 70 sa0 tbd fbga bit# signal name pin id fbga bit# signal name pin id 1 sa tbd 2 sa tbd 3 sa tbd 4 sa tbd 5 sa tbd 6 sa tbd 7 sa tbd 8 nc/ dqpa tbd 9 dqa tbd 10 dqa tbd 11 dqa tbd 12 dqa tbd 13 dqa tbd 14 dqa tbd 15 dqa tbd 16 dqa tbd 17 zz tbd 18 dqb tbd 19 dqb tbd 20 dqb tbd 21 dqb tbd 22 dqb tbd 23 dqb tbd 24 dqb tbd 25 dqb tbd 26 nc/ dqpb tbd 27 sa tbd 28 sa tbd 29 adv# tbd 30 adsp# tbd 31 adsc# tbd 32 oe# (g#) tbd 33 bwe# tbd 34 gw# tbd 35 clk tbd
31 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance fbga part marking guide sdk pc product family s = sram m = sram mechanical sample x = sram engineering sample product type b = qdr burst of 2 c = qdr burst of 4 d = ddr f = syncburst , pipelined, single-cycle deslect g = syncburst, pipelined, double-cycle deslect h = syncburst, flow-through j = zbt , pipelined k = zbt, flow-through density b = 2mb, 3.3v v dd c = 2mb, 2.5v v dd d = 2mb, 1.8v v dd f = 4mb, 3.3v v dd g = 4mb, 2.5v v dd h = 4mb, 1.8v v dd j = 8mb, 3.3v v dd k = 8mb, 2.5v v dd l = 8mb, 1.8v v dd m = 16mb, 3.3v v dd n = 16mb, 2.5v v dd p = 16mb, 1.8v v dd width b = x18, 3.3v v dd q c = x18, 2.5v v dd q d = x18, 3.3v & 2.5v v dd q f = x18, hstl v dd q g = x32, 3.3v v dd q h = x32, 2.5v v dd q j = x32, 3.3v & 2.5v v dd q k = x32, hstl v dd q l = x36, 3.3v v dd q m = x36, 2.5v v dd q n = x36, 3.3v & 2.5v v dd q p = x36, hstl v dd q q = x72, 3.3v v dd q r = x72, 2.5v v dd q s = x72, 3.3v & 2.5v v dd q t = x72, hstl v dd q speed grade b=-3 c = -3.3 d=-4 f = -4.4 g=-5 h=-6 j=-7 k = -7.5 q = 32mb, 3.3v v dd r = 32mb, 2.5v v dd s = 32mb, 1.8v v dd t = 64mb, 3.3v v dd v = 64mb, 2.5v v dd w = 64mb, 1.8v v dd x = 128mb, 3.3v v dd y = 128mb, 2.5v v dd z = 128mb, 1.8v v dd l=-8 m = -8.5 n=-9 p = -9.5 q = -10 r = -10.5 s = -11 t = -12 qdr rams and quad data rate rams comprise a new family of products developed by cypress semiconductor, idt, and micron technology, inc. zbt and zero bus turnaround are trademarks of integrated device technology, inc., and the architecture is supported by micron technology, inc., and motorola inc.
32 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance 100-pin plastic tqfp (jedec lqfp) 14.00 0.10 20.10 0.10 0.62 22.10 +0.10 -0.15 16.00 +0.20 -0.05 pin #1 id 0.65 1.50 0.10 0.25 0.60 0.15 1.40 0.05 0.32 +0.06 -0.10 0.15 +0.03 -0.02 0.10 +0.10 -0.05 detail a detail a 1.00 (typ) gage plane 0.10 note: 1. all dimensions in millimeters max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
33 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance 165-pin fbga note: 1. all dimensions in millimeters max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 10.00 14.00 15.00 0.10 1.00 (typ) 1.00 (typ) 5.00 0.05 13.00 0.10 pin a1 id pin a1 id mold compound: epoxy novolac substrate: plastic laminate 6.50 0.05 7.00 0.05 7.50 0.05 1.20 max solder ball material: eutectic 63% sn, 37% pb solder ball pad: ? .33mm seating plane 0.85 0.075 0.10 a a typ .45 +.05 -.10 ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 syncburst is a trademark and micron is a registered trademark of micron technology, inc. pentium is a registered trademark of intel corporation.
34 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or s pecifications without notice. MT58L1MY18D_2.p65 C rev 7/00 ?2000, micron technology, inc. 16mb: 1 meg x 18, 512k x 32/36 pipelined, dcd syncburst sram advance revision history changed fbga capacitance values, rev. 7/00, advance ............................................................................ ... aug/8/00 c i ; typ 2.5 pf from 4 pf; max 3.5 pf from 5 pf c o ; typ 4 pf from 6 pf; max 5 pf from 7 pf c ck ; typ 2.5 pf from 5 pf; max 3.5 pf from 6 pf removed industrial temperature references, rev. 7/00, advance .............................................................. july /24/00 added 165-pin fbga package, rev. 7/00, advance ................................................................................. ... jun/28/00 added fbga part marking references removed 119-pin pbga and references added note: it available for -8.5 and -10 speed grades change pin 14 to nc from v dd , rev. 4/00, advance .................................................................................. apr/13/00 added note: zz has internal pull-down updated boundary scan order, rev. 3/00, advance ................................................................................ ..... apr/6/00 added advance status, rev. 1/00, advance ....................................................................................... ....... jan/18/00 MT58L1MY18D, rev. 11/99, advance ........................................................................................................ nov/11/99 added bga jtag functionality

▲Up To Search▲

Price & Availability of MT58L1MY18D

	To Download MT58L1MY18D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .